As communication devices become more complex, they typically have larger power requirements. This, in part, is due to complex software requiring the processor to operate for long periods of time and/or at a higher clock rate. Both conditions causing the processor to draw more current. In a portable, battery powered device, this depletes the battery's power quicker.
The processor in a communication device such as a radiotelephone performs processes to generate the bit error rate (BER) of user information and control signals transmitted from the base station. The EIA/TIA specification uses user information to denote the speech parameters generated by the vocoder. The BER can be used by the processor to mute audio, as a display indication, FACCH or user information determination, and channel quality estimation.
The control signals are transmitted over a control channel that is referred to in the art as a Fast Associated Control Channel (FACCH). This channel is a blank-and-burst channel for signalling message exchange between the base station and the mobile station.
FACCH decoding is performed before user information decoding. This is due to the lack of robustness in the cyclic redundancy check (CRC) performed after user information decoding to determine the validity of the user information; FACCH data will be mistaken for user information, thus losing the FACCH message.
FACCH and user information convolutionally encoded data share the same location during transmission, therefore only one message type can be present at any one time. Because user information convolutionally encoded data is transmitted more frequently than FACCH convolutionally encoded data, the execution of the FACCH decoding algorithms before the user information decoding algorithms becomes wasteful of instruction cycles and thus current drain. It is unknown whether a FACCH message or user information is going to be received. Therefore, both must be checked using million instructions per second (MIPS) exhaustive algorithms.
As discussed above, the BER estimation process is an important one that requires a large number of MIPS. Reducing this requirement would reduce the current requirement of the processor in addition to freeing the processor to do other tasks. There is a resulting need for a process to estimate the BER of a signal using a minimum amount of processor time.